As integration circuits (ICs) are developed toward very-large-scale integration (VLSI) circuits, the density of circuits in the ICs increases. The number of components included in ICs also becomes larger and larger, and accordingly, the sizes of the components are reduced. As the most fundamental semiconductor devices, transistors have been widely used in ICs. With the increase of the device density and the integration level of semiconductor devices, the sizes of the transistors also decrease. Therefore, the distance between the source, the drain, and the gate of the transistors becomes smaller and smaller.
Moreover, as the density of the circuits increases, the wafer surface may not be able to provide enough area for the fabrication of connection wires. As the size of the device becomes smaller, in order to meet the requirements on interconnections, the design of double-layer or multiple-layer metal interconnection wires becomes one of the methods that are commonly used in VLSI technology. The connections between different metal layers or between metal layers and semiconductor devices may be realized through plugs.
In the meantime, as the process node of ICs becomes smaller, the distance between the source, the drain, and the gate of the transistor gradually decreases, resulting in an increase in the processing difficulty for forming the plugs on the source, the drain, and the gate of the transistor. For example, it may not be able to directly form contact holes through photolithography and etching processes. Therefore, a self-aligned process is introduced into the process for forming the plugs.
However, a semiconductor structure containing plugs formed by the self-aligned process may often have an overly large parasitic capacitance, which may further lead to degraded performance of the formed semiconductor structure. The disclosed semiconductor structures and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.